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6
LTC1427-50
TI I G DIAGRA S
U
W
Timing for SMBus Interface
tBUF
tLOW
tHIGH
tr
tf
tHD:STA
tHD:DAT
SDA
SCL
tSU:DAT
tSU:STA
tSU:STO
STOP
1427 TD01
START
STOP
tHD:STA
APPLICATIONS INFORMATION
WU
U
Digital Interface
The LTC1427-50 communicates with an SMBus host
using the standard 2-wire SMBus interface. The Timing
Diagram shows the signals on the SMBus. The SCL and
SDA bus lines must be high when the bus is not in use.
External pull-up resistors or current sources are required
at these lines.
The LTC1427-50 is a receive-only (slave) device. The
master must apply the following Write Byte protocol to
communicate with the LTC1427-50:
1
7
1
181
8
1
S Slave Address WR
A
Command Byte
A
Data Byte
A P
S = Start Condition, WR = Write Bit, A = Acknowledge Bit, P = Stop Condition
IOUT
SCL
S = START
P = STOP
* = OPTIONAL
SDA
AD0
S
1
0
2
1
3
0
4
1
5
1
6
1
7
1
XX
X
1
8
9
10
WR
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
P
FULL-SCALE
CURRENT
VCC
GND
VCC
GND
1427 TD02
ZERO-SCALE
CURRENT
*
SHDN
ACK
SMBUS ADDRESS
COMMAND BYTE
DATA BYTE
AD1
Operating Sequence
SMBus Write Byte Protocol, with SMBus Address = 0101111B,
Command Byte = 0XXXXX11B and Data Byte = 11111111B
The master initiates communication with the LTC1427-50
with a START condition (see SMBus Operating Sequence)
and a 7-bit address followed by the write bit = 0. The
LTC1427-50 acknowledges and the master delivers the
command byte. The LTC1427-50 acknowledges and latches
the active bits of the command byte into register A (see
Block Diagram) at the falling edge of the acknowledge
pulse. The master sends the data byte and the LTC1427-
50 acknowledges the data byte. The data byte and last two
output bits from register A are latched into register C at the
falling edge of the final acknowledge pulse and the DAC
current output assumes the new 10-bit data value (see
Block Diagram). A STOP condition is optional. The com-
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